This invention is in the field of electronic systems incorporating embedded ferroelectric memory resources. Embodiments are directed to such systems and methods of operating the same to update the contents of those embedded memory resources.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have recently been developed.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example by placing the capacitors above the transistor level, between overlying levels of metal conductors.
FIG. 1 illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage +Vα, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage −Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the difference in capacitance exhibited by a ferroelectric capacitor between its polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. In the context of a ferroelectric capacitor, the change in polarization state that occurs upon application of a polarizing voltage is reflected in charge storage. For example, referring to FIG. 1, the polarization of a ferroelectric capacitor from its “−1” state to its “+1” state is reflected in a relatively high capacitance C(−1), by way of which polarization charge involved in the change of polarization state is retained within the capacitor as the voltage exceeds its coercive voltage Vα; on the other hand, a capacitor already in its “+1” state exhibits little capacitance C(+1) due to polarization, since its ferroelectric domains are already aligned prior to the application of the voltage. In each case, the ferroelectric capacitor also has a linear capacitance, by virtue of its construction as parallel plates separated by a dielectric film (i.e., the ferroelectric material). As will be evident from the following description, a stored logic state is read by interrogating the capacitance of ferroelectric capacitors to discern its polarized state.
Ferroelectric technology is now used to realize non-volatile solid-state read/write random access memories (RAMs). These memory resources, commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM”, are now commonplace in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers, defibrillators, and monitoring devices, due to the ultra-low power consumption of FRAM memory.
One approach to the implementation of FRAMs is the two-transistor, two-capacitor (2T2C) ferroelectric memory cell, in which the two ferroelectric capacitors in a cell are polarized to complementary states. FIG. 2a schematically illustrates memory cell 2j,k of conventional 2T2C construction. In this example, cell 2j,k resides in a row j and a column k of a memory array, and includes two ferroelectric capacitors 4a, 4b and two metal-oxide semiconductor (MOS) transistor 5a, 5b. Ferroelectric capacitors 4a, 4b are parallel-plate capacitors with ferroelectric material, such as PZT, as the dielectric; one or both of the plates may be formed in semiconductor material (e.g., a diffused region in the substrate, polysilicon, etc.) or in a metal or conductive metal compound material (e.g., a silicide, or conductive nitride). One plate of each of ferroelectric capacitors 4a, 4b is connected to plate line PLj for row j. The other plate of ferroelectric capacitor 4a is connected to bit line BLTk for column k via the source/drain path of p-channel transistor 5a; similarly, the second plate of ferroelectric capacitor 4b is connected to bit line BLCk via the source/drain path of n-channel transistor 5b. The gates of transistors 5a, 5b are driven by word line WLj for row j of the memory array.
In operation, ferroelectric capacitors 4a, 4b store complementary polarization states that are reflected as a differential voltage or current between bit lines BLTk, BLCk when read. As such, a write operation to conventional memory cell 2j,k consists of applying complementary levels to bit lines BLTk, BLCk at a polarity corresponding to the desired data state, while word line WLj is driven active high to turn on transistors 5a, 5b; a pulse at plate line PLj during this state causes opposite polarization voltages to polarize capacitors 4a, 4b into the corresponding complementary polarization states. In a read operation, bit lines BLTk, BLCk are precharged to a selected voltage and then float, after which word line WLj is asserted active high. A pulse at plate line PLj causes the complementary polarization states of capacitors 4a, 4b to be reflected as a differential signal across bit lines BLTk, BLCk, respectively, for sensing and amplification by sense amplifier 6k for column k.
FIG. 2b illustrates, in block form, a simplified arrangement of conventional memory array 5 of memory cells 2 such as constructed according to FIG. 2a. Of course, memory arrays in actual integrated circuits are much larger than that shown in FIG. 3; this small (4 by 4) example is provided for illustration only. In array 5 of FIG. 3, each row of cells 2 in the array is associated with a corresponding one of word lines WL0 through WL3 and one of plate lines PL0 through PL3. Each column of cells 2 share a pair of bit lines, with column 0 coupled to bit lines BLT0, BLC0; column 1 coupled to bit lines BLT1, BLC1, and so on. Sense amplifier 60 receives bit lines BLT0, BLC0, sense amplifier 61 receives bit lines BLT1, BLC1, sense amplifier 62 receives bit lines BLT2, BLC2, and sense amplifier 63 receives bit lines BLT3, BLC3. Accordingly, the energizing of word line WLj and plate line PLj for row j of cells 2 will cause the read or write (as the case may be) of data from or to cells 2j,0 through 2j,3, via bit lines pairs BLT0, BLC0 through BLT3, BLC3, respectively.
The conventional 2T2C arrangement of FIGS. 2a and 2b has been observed to provide good long term data retention because of the robust read margin resulting from the differential sense arrangement. Even if one of ferroelectric capacitors 4a, 4b in a given cell 2j,k is weak when manufactured, or suffers a significant loss of polarization during the operating life of the device, the cell can still return the correct data state so long as the opposing capacitor retains a stronger polarized state.
In contrast, ferroelectric cells constructed in a 1T1C (one transistor, one capacitor) arrangement, similar to conventional dynamic RAM memory cells, are attractive because of their small chip area. FIG. 2c illustrates a typical arrangement of a conventional 1T-1C FRAM cell 12jk, which represents a single cell residing in a row j and a column k of an array of similar cells 12. Cell 12jk includes ferroelectric capacitor 14 and n-channel pass transistor 15. The source/drain path of transistor 15 is connected between bit line BLk for column k of the array, and the top plate of ferroelectric capacitor 14; the gate of transistor 15 is controlled by word line WLj for row j of the array. The bottom plate of ferroelectric capacitor 14 is connected to plate line PL for the row, or which may be in common for all cells 12 in the array or array portion, depending on the architecture. As such, 1T-1C FRAM cells are constructed similarly as conventional dynamic RAM memory cells. Sense amplifier 16k is coupled to bit line BLk, and operates to compare the bit line voltage developed by read current iR to a reference voltage VREF generated by a reference voltage generator, or at a “dummy” bit line as may be produced by a reference capacitor, as known in the art. This reference voltage VREF is typically at an intermediate level between the expected voltages for the “0” and “1” data states.
In comparing the 1T1C and 2T2C FRAM cell architectures, the 1T1C cell has the advantage of increased bit density but the disadvantage of reduced read margin because of its single-ended sense relative to a reference voltage, while the 2T2C cell provides the advantage of robust data retention from complementary data storage and differential sensing, but at only about one-half the bit density.
As mentioned above, FRAM non-volatile memory has become popular for use in many electronic systems. So-called “system-on-a-chip” (SoC) devices, such as the MSP430 family of microcontrollers available from Texas Instruments Incorporated, now often include FRAM resources, particularly when used to realize sensors and controllers deployed in remote locations and thus in which power consumption is a particular concern. Zwerg et al., “An 82 mA/MHz Microcontroller with Embedded FeRAM for Energy-Harvesting Applications”, Digest of Technical Papers, 2011 Int'l Solid-State Circ. Conf., paper 19.2 (IEEE), pp. 334-36, incorporated herein by this reference, describes an example of such a microcontroller-based SoC. The networking of these and similar SoC devices according to the so-called “Internet of Things” (IoT) is becoming widespread.
Particularly in those networked implementations, FRAM is often used to store the microcontroller “firmware”, including executable program code according to which the particular sensor or controller carries out its desired function. Considering the expected system life of these remotely-deployed IoT devices, SoC architectures typically include some provision for updating that system firmware, including the ability to verify the newly-received updated firmware prior to its installation to ensure post-update operability. In conventional architectures, a buffer in the memory space is necessary to store the updated firmware during this verification, prior to overwriting the existing firmware image in FRAM. Of course, this buffer necessitates the realization of additional memory in the SoC device, which increases the chip area and thus the manufacturing cost of the device, as well as potentially impacting the power consumption of the SoC. In some system architectures, an additional memory device (e.g., RAM), external to the SoC device, is provided as a buffer for storing updated firmware prior to validation. While avoiding the cost of implementing the additional buffer in the SoC device, this external buffer of course increases the cost and complexity of the overall system.
By way of further background, FRAM architectures in which the memory cells can be selectively operated in either of the 2T2C or 1T1C modes are known in the art. An example of such an architecture is described in U.S. Pat. No. 5,571,628, incorporated herein by reference. In the example of U.S. Pat. No. 5,571,628, a control signal selects whether an additional row address line is to be decoded, in which case the FRAM cells are operated (i.e., written and read) as 1T1C cells. For a read cycle in the 1T1C mode, a dummy word line is activated to couple a reference memory cell capacitor to the opposite bit line from that to which the addressed 1T1C cell is coupled; the sense amplifier then senses the data state of the addressed 1T1C cell by comparison with the bit line voltage produced by the reference memory cell capacitor. Conversely, for a read cycle in the 2T2C mode, the dummy word line is not activated; rather, two word lines are activated to couple cells in adjacent rows and the same column to opposing bit lines, for differential sensing by the sense amplifier.